ilang  1.0.2
ILAng: A Modeling and Verification Platform for SoCs
verilog_gen.h
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1 
11 #ifndef ILANG_VERILOG_OUT_VERILOG_GEN_H__
12 #define ILANG_VERILOG_OUT_VERILOG_GEN_H__
13 
14 #include <list>
15 #include <map>
16 #include <unordered_map>
17 #include <vector>
18 
20 
22 namespace ilang {
23 
24 typedef ExprHash VerilogGenHash;
25 class VlgSglTgtGen;
26 class VlgVerifTgtGen;
27 class IntefaceDirectiveRecorder;
28 class TestVerilogExport;
29 
32 public:
33  // --------------------- TYPE DEFINITIONS ---------------------------- //
35  using IlaBoolValType = bool;
41  friend class TestVerilogExport;
43  friend class VlgSglTgtGen;
48  typedef struct {
50  std::string raddr;
52  std::string rdata;
54  std::string ren;
55  } rport_t;
57  typedef struct {
59  std::string waddr;
61  std::string wdata;
63  std::string wen;
64  } wport_t;
65 
67  typedef std::string vlg_name_t;
69  typedef std::string vlg_stmt_t;
71  typedef std::string vlg_const_t;
73  typedef std::string vlg_addr_t;
75  typedef std::string vlg_data_t;
77  typedef std::vector<vlg_name_t> vlg_stmts_t;
79  typedef std::vector<vlg_name_t> vlg_names_t;
81  typedef std::pair<vlg_name_t, int> vlg_sig_t;
83  typedef std::vector<vlg_sig_t> vlg_sigs_t;
85  typedef std::map<vlg_name_t, int> vlg_sigs_map_t;
87  typedef std::map<vlg_name_t, bool> vlg_sig_keep_t;
89  typedef std::set<vlg_sig_t> vlg_sigs_set_t;
91  typedef std::tuple<vlg_stmt_t, vlg_stmt_t, vlg_stmt_t> vlg_ite_stmt_t;
93  typedef std::vector<vlg_ite_stmt_t> vlg_ite_stmts_t;
95  typedef std::tuple<vlg_name_t, int, int, int>
96  vlg_mem_t; // name addr_width data_width entryNum
98  typedef std::map<vlg_name_t, vlg_mem_t> vlg_mems_rec_t;
101  ExprPtr addr;
102  ExprPtr data;
103  };
105  typedef std::list<mem_write_entry_t> mem_write_entry_list_t;
107  typedef std::list<mem_write_entry_list_t> mem_write_entry_list_stack_t;
109  struct mem_write_t {
110  ExprPtr cond;
111  mem_write_entry_list_t writes;
112  };
114  typedef std::list<mem_write_t> mem_write_list_t;
115 
117  struct function_app_t {
119  std::vector<vlg_sig_t> args;
123  const std::string func_name;
125  function_app_t(const vlg_sig_t& res, const std::string fn)
126  : result(res), func_name(fn) {}
127  }; // struct function_app_t
128  typedef std::vector<function_app_t> function_app_vec_t;
129 
134  // you don't need the value
135  state_update_unknown(const vlg_name_t & c) : condition(c) {}
136  }; // struct state_update_unknown
137  typedef std::map<std::string, state_update_unknown> state_update_ite_unknown_map_t;
138 
140  typedef std::unordered_map<const ExprPtr, vlg_name_t, VerilogGenHash> ExprMap;
142  // (this is needed because our hash is not fully working)
143  typedef std::map<std::pair<IlaBvValType, unsigned>, vlg_name_t> CnstMap;
145  typedef std::map<std::string, bool> memory_export_annotation_t;
146 
147  // VerilogGen Configure
148 public:
150  struct VlgGenConfig {
153  bool extMem;
155  enum funcOption { Internal, External } fcOpt;
161  bool reg_random_init; // this is also to avoid Yosys optimization
167 
170  VlgGenConfig( // provide the default settings
171  bool ExternalMem = true, funcOption funcOpt = funcOption::Internal,
172  bool gen_start = false, bool pass_name = false, bool rand_init = false,
173  bool ExpandMem = false, bool CollectIteUnknownUpdate = false)
174  : extMem(ExternalMem), fcOpt(funcOpt), start_signal(gen_start),
175  pass_node_name(pass_name), reg_random_init(rand_init),
176  expand_mem(ExpandMem), collect_ite_unknown_update(CollectIteUnknownUpdate) {}
178  VlgGenConfig(const VlgGenConfig& c, bool ExternalMem, funcOption funcOpt,
179  bool gen_start, bool rand_init, bool ExpandMem, bool CollectIteUnknownUpdate)
180  : extMem(ExternalMem), fcOpt(funcOpt), start_signal(gen_start),
182  expand_mem(ExpandMem), collect_ite_unknown_update(CollectIteUnknownUpdate) {}
183  // set other fields if there are such need (?)
184  }; // end of struct VlgGenConfig
185 
186  // --------------------- HELPER for DEBUG PURPOSE ----------------------------
187  //
188  friend std::ostream& operator<<(std::ostream& out,
189  const mem_write_entry_t& mwe);
190  friend std::ostream& operator<<(std::ostream& out,
191  const mem_write_entry_list_t& mwel);
192  friend std::ostream& operator<<(std::ostream& out,
193  const mem_write_entry_list_stack_t& mwel);
194  friend std::ostream& operator<<(std::ostream& out, const mem_write_t& mw);
195  friend std::ostream& operator<<(std::ostream& out,
196  const mem_write_list_t& mwl);
197 
198  // --------------------- MEMBERS ---------------------------- //
199 protected:
200  // --------------------- Verilog related ---------------------------- //
258  ite_stmts; // this stmt is only used in sequential always block
266 
272 
277  std::map<std::string, std::map<unsigned, rport_t>> ila_rports;
279  std::map<std::string, std::map<unsigned, wport_t>> ila_wports;
281  function_app_vec_t ila_func_app;
283  state_update_ite_unknown_map_t state_update_ite_unknown;
284  // Annotations
285  memory_export_annotation_t memory_export_annotation;
286 
287  // --------------------- HELPER FUNCTIONS ---------------------------- //
289  bool check_reserved_name(const vlg_name_t& n) const;
291  int static get_width(const ExprPtr& n);
293  std::string static WidthToRange(int w);
295  vlg_name_t new_id();
298  vlg_name_t new_id(const ExprPtr& e);
299 
300 public:
302  static vlg_name_t sanitizeName(const vlg_name_t& n);
305  static vlg_name_t sanitizeName(const ExprPtr& n);
307  static vlg_const_t ToVlgNum(IlaBvValType value, unsigned width);
308 
309 protected:
311  unsigned idCounter;
315  std::map<std::string, std::string> reference_name_set;
318  std::set<FuncPtr> func_ptr_set;
319 
320  // --------------------- HELPER FUNCTIONS ---------------------------- //
321 public:
323  void add_input(const vlg_name_t& n, int w);
325  void add_output(const vlg_name_t& n, int w);
327  void add_wire(const vlg_name_t& n, int w, bool keep = false);
329  void add_reg(const vlg_name_t& n, int w);
331  void add_stmt(const vlg_stmt_t& s);
333  void add_assign_stmt(const vlg_name_t& l, const vlg_name_t& r);
336  void add_always_stmt(const vlg_stmt_t& s);
338  void add_init_stmt(const vlg_stmt_t& s);
341  void add_ite_stmt(const vlg_stmt_t& cond, const vlg_stmt_t& tstmt,
342  const vlg_stmt_t& fstmt);
344  void add_internal_mem(const vlg_name_t& mem_name, int addr_width,
345  int data_width, int entry_num);
347  void add_external_mem(const vlg_name_t& mem_name, int addr_width,
348  int data_width, int entry_num);
350  void add_preheader(const vlg_stmt_t& stmt);
351 
352 public:
353  // --------------------- CONSTRUCTOR ---------------------------- //
359  const std::string& modName = "",
360  const std::string& clk = "clk",
361  const std::string& rst = "rst");
362 
365  virtual void DumpToFile(std::ostream& fout) const;
366 
367  // --------------------- ANNOTATION INTERFACE ---------------------------- //
369  void AnnotateMemory(const memory_export_annotation_t& annotation);
370 }; // class VerilogGeneratorBase
371 
374 public:
375  // --------------------- TYPE DEFINITIONS ---------------------------- //
377  friend class TestVerilogExport;
419  // VerilogGen Configure
425  using function_app_vec_t = VerilogGeneratorBase::function_app_vec_t;
426 
427 private:
428  // --------------------- HELPER FUNCTIONS ---------------------------- //
430  void insertInput(const ExprPtr& input);
432  void insertState(const ExprPtr& state);
433 
434  // Here we are not using depthfirstSearch as we need to alternate between
435  // root-first/root-last traversal
437  void parseArg(const ExprPtr& e);
440  VerilogGenerator::vlg_name_t getVlgFromExpr(const ExprPtr& e);
442  VerilogGenerator::vlg_name_t getArg(const ExprPtr& e, const size_t& i);
444  vlg_name_t translateApplyFunc(std::shared_ptr<ExprOpAppFunc> func_app_ptr_);
446  vlg_name_t translateBoolOp(const std::shared_ptr<ExprOp>& e);
448  vlg_name_t translateBvOp(const std::shared_ptr<ExprOp>& e);
450  void ParseNonMemUpdateExpr(const ExprPtr& e);
452  bool CheckMemUpdateNode(const ExprPtr& e, const std::string& mem_var_name);
455  void VisitMemNodes(const ExprPtr& e, const ExprPtr& cond,
456  mem_write_entry_list_stack_t& writesStack);
457 
460  void addInternalCounter(vlg_name_t decode_sig_name, size_t width = 8);
462  void ExportFuncDefs();
463 
465  void ExportCondWrites(const ExprPtr& mem_var,
466  const mem_write_list_t& writeList);
469  void ParseMemUpdateNode(const ExprPtr& cond, const ExprPtr& e,
470  const std::string& mem_var_name);
471 
472 public:
473  // --------------------- CONSTRUCTOR ---------------------------- //
478  VerilogGenerator(const VlgGenConfig& config = VlgGenConfig(),
479  const std::string& modName = "",
480  const std::string& clk = "clk",
481  const std::string& rst = "rst");
483  void ExportIla(const InstrLvlAbsPtr& ila_ptr_);
485  void ExportTopLevelInstr(const InstrPtr& instr_ptr_);
486 }; // class VerilogGenerator
487 
488 }; // namespace ilang
489 
490 #endif // ILANG_VERILOG_OUT_VERILOG_GEN_H__
ilang::VerilogGeneratorBase::VlgGenConfig::expand_mem
bool expand_mem
Definition: verilog_gen.h:164
ilang::VerilogGeneratorBase::add_wire
void add_wire(const vlg_name_t &n, int w, bool keep=false)
record a wire
ilang::VerilogGeneratorBase::all_valid_names
vlg_sigs_set_t all_valid_names
to hold all valid names, a sanity check
Definition: verilog_gen.h:274
ilang::VerilogGeneratorBase::VlgGenConfig::start_signal
bool start_signal
whether to have the start signal
Definition: verilog_gen.h:157
ilang::VerilogGeneratorBase::state_update_unknown
Type of ite update unknown.
Definition: verilog_gen.h:131
ilang::VerilogGeneratorBase::CnstMap
std::map< std::pair< IlaBvValType, unsigned >, vlg_name_t > CnstMap
Type for cacheing the constant.
Definition: verilog_gen.h:143
ilang::VerilogGeneratorBase::vlg_mems_rec_t
std::map< vlg_name_t, vlg_mem_t > vlg_mems_rec_t
Type of collection of memorys.
Definition: verilog_gen.h:98
ilang::VerilogGeneratorBase::vlg_data_t
std::string vlg_data_t
Type of Verilog data.
Definition: verilog_gen.h:75
ilang::VerilogGeneratorBase::nmap
ExprMap nmap
The map to cache the expression (we only need to store the name)
Definition: verilog_gen.h:262
ilang::VerilogGeneratorBase::VlgGenConfig::collect_ite_unknown_update
bool collect_ite_unknown_update
whether to collect the ite(c, v, unknown) thing
Definition: verilog_gen.h:166
ilang::VerilogGeneratorBase::vlg_sig_keep_t
std::map< vlg_name_t, bool > vlg_sig_keep_t
Type of a map: name -> need to add keep?
Definition: verilog_gen.h:87
ilang::VerilogGeneratorBase::cmap
CnstMap cmap
Definition: verilog_gen.h:265
ilang::ExprPtr
Expr::ExprPtr ExprPtr
Pointer type for normal use of Expr.
Definition: expr.h:133
ilang::VerilogGeneratorBase::ite_stmts
vlg_ite_stmts_t ite_stmts
Definition: verilog_gen.h:258
ilang::VerilogGenerator::VlgGenConfig
VerilogGeneratorBase::VlgGenConfig VlgGenConfig
the structure to configure the verilog generator
Definition: verilog_gen.h:421
ilang::VerilogGeneratorBase::VlgGenConfig
the structure to configure the verilog generator
Definition: verilog_gen.h:150
ilang::VerilogGeneratorBase::add_always_stmt
void add_always_stmt(const vlg_stmt_t &s)
ilang::VerilogGeneratorBase::statements
vlg_stmts_t statements
statements to be outside the always block
Definition: verilog_gen.h:252
ilang::VerilogGenerator::TestVerilogExport
friend class TestVerilogExport
let the test class use this module
Definition: verilog_gen.h:377
ilang::VerilogGeneratorBase::regs
vlg_sigs_t regs
vector of regs to be defined
Definition: verilog_gen.h:240
ilang::VerilogGeneratorBase
Base class of VerilogGenerator.
Definition: verilog_gen.h:31
ilang::VerilogGeneratorBase::mem_write_entry_list_stack_t
std::list< mem_write_entry_list_t > mem_write_entry_list_stack_t
Type of a stack of writes use in visitMemNodes.
Definition: verilog_gen.h:107
ilang::VerilogGenerator::ExportTopLevelInstr
void ExportTopLevelInstr(const InstrPtr &instr_ptr_)
Parse an instruction.
ilang::VerilogGeneratorBase::vlg_ite_stmt_t
std::tuple< vlg_stmt_t, vlg_stmt_t, vlg_stmt_t > vlg_ite_stmt_t
Type of Verilog ITEs (IN sequential block)
Definition: verilog_gen.h:91
ilang::VerilogGeneratorBase::validName
vlg_name_t validName
Definition: verilog_gen.h:212
ilang::VerilogGeneratorBase::mems_external
vlg_mems_rec_t mems_external
vector of mems from outside (will not be defined)
Definition: verilog_gen.h:244
ilang::VerilogGeneratorBase::add_stmt
void add_stmt(const vlg_stmt_t &s)
record a stmt (outside the always block)
ilang::VerilogGeneratorBase::add_ite_stmt
void add_ite_stmt(const vlg_stmt_t &cond, const vlg_stmt_t &tstmt, const vlg_stmt_t &fstmt)
ilang::VerilogGeneratorBase::vlg_addr_t
std::string vlg_addr_t
Type of Verilog address.
Definition: verilog_gen.h:73
ilang::VerilogGeneratorBase::idCounter
unsigned idCounter
The id counter.
Definition: verilog_gen.h:311
ilang::VerilogGeneratorBase::func_ptr_set
std::set< FuncPtr > func_ptr_set
Definition: verilog_gen.h:318
ilang::VerilogGeneratorBase::startName
vlg_name_t startName
start signal name, may not be used
Definition: verilog_gen.h:214
ilang::VerilogGeneratorBase::IlaBoolValType
bool IlaBoolValType
The type of bool value in ila.
Definition: verilog_gen.h:35
ilang::VerilogGeneratorBase::ila_rports
std::map< std::string, std::map< unsigned, rport_t > > ila_rports
Definition: verilog_gen.h:277
ilang::VerilogGeneratorBase::DumpToFile
virtual void DumpToFile(std::ostream &fout) const
ilang::VerilogGeneratorBase::add_assign_stmt
void add_assign_stmt(const vlg_name_t &l, const vlg_name_t &r)
record an assignment stmt (outside the always block), will call add_stmt
ilang::VerilogGeneratorBase::mem_i
vlg_sigs_t mem_i
vector of memory input signals
Definition: verilog_gen.h:230
ilang::VerilogGeneratorBase::sanitizeName
static vlg_name_t sanitizeName(const vlg_name_t &n)
sanitize a name string, so it will generate illegal verilog identifier
ilang::VerilogGeneratorBase::decodeAccName
vlg_sig_t decodeAccName
accumulated decode signals
Definition: verilog_gen.h:222
ilang::VlgSglTgtGen
Generating a target (just the invairant or for an instruction)
Definition: vtarget_gen_impl.h:36
ilang::VerilogGeneratorBase::VlgGenConfig::funcOption
funcOption
whether to treat function as internal module/external module
Definition: verilog_gen.h:155
ilang::VerilogGeneratorBase::mem_write_entry_list_t
std::list< mem_write_entry_t > mem_write_entry_list_t
This is type of a list of writes.
Definition: verilog_gen.h:105
ilang::VerilogGeneratorBase::mem_write_list_t
std::list< mem_write_t > mem_write_list_t
List of writes w. associated conditions.
Definition: verilog_gen.h:114
ilang::VerilogGeneratorBase::WidthToRange
static std::string WidthToRange(int w)
convert a widith to a verilog string
ilang::VerilogGeneratorBase::vlg_stmts_t
std::vector< vlg_name_t > vlg_stmts_t
Type of Verilog statements (a vector)
Definition: verilog_gen.h:77
ilang::VerilogGeneratorBase::VlgGenConfig::reg_random_init
bool reg_random_init
whether to give random init to the register
Definition: verilog_gen.h:161
ilang::VerilogGeneratorBase::vlg_name_t
std::string vlg_name_t
Type of Verilog id names.
Definition: verilog_gen.h:67
ilang::VerilogGeneratorBase::add_internal_mem
void add_internal_mem(const vlg_name_t &mem_name, int addr_width, int data_width, int entry_num)
record an internal memory
ilang::VerilogGeneratorBase::mem_o
vlg_sigs_t mem_o
vector of memory output signals
Definition: verilog_gen.h:232
ilang::VerilogGeneratorBase::mem_write_entry_t
This is type of an individual write.
Definition: verilog_gen.h:100
ilang::VerilogGeneratorBase::rstName
vlg_name_t rstName
Reset signal name.
Definition: verilog_gen.h:206
ilang::VerilogGeneratorBase::vlg_mem_t
std::tuple< vlg_name_t, int, int, int > vlg_mem_t
Type of the memorys that are going to be created.
Definition: verilog_gen.h:96
ilang::VerilogGeneratorBase::rport_t::rdata
std::string rdata
what to connect for rdata
Definition: verilog_gen.h:52
ilang::VerilogGeneratorBase::mem_probe_o
vlg_sigs_t mem_probe_o
vector of signals that probe each element of a memory
Definition: verilog_gen.h:234
ilang::VerilogGeneratorBase::rport_t::raddr
std::string raddr
what to connect for raddr
Definition: verilog_gen.h:50
ilang::VerilogGeneratorBase::mems_internal
vlg_mems_rec_t mems_internal
vector of mems to be defined
Definition: verilog_gen.h:242
ilang::VerilogGeneratorBase::wport_t::waddr
std::string waddr
what to connect for waddr
Definition: verilog_gen.h:59
ilang::VerilogGeneratorBase::current_writes
mem_write_list_t current_writes
For traverse a mem expression.
Definition: verilog_gen.h:268
ilang::VerilogGeneratorBase::vlg_const_t
std::string vlg_const_t
Type of Verilog constants.
Definition: verilog_gen.h:71
ilang::IntefaceDirectiveRecorder
Used in Verilog Verification Target Generation for dealing with interface directives.
Definition: directive.h:28
ilang::VerilogGenerator::ExportIla
void ExportIla(const InstrLvlAbsPtr &ila_ptr_)
Parse an ILA, will gen all its instructions.
ilang::VerilogGeneratorBase::vlg_sigs_t
std::vector< vlg_sig_t > vlg_sigs_t
Type of Verilog signals (a vector)
Definition: verilog_gen.h:83
ilang::VerilogGeneratorBase::VerilogGeneratorBase
VerilogGeneratorBase(const VlgGenConfig &config=VlgGenConfig(), const std::string &modName="", const std::string &clk="clk", const std::string &rst="rst")
ilang::VerilogGeneratorBase::ila_func_app
function_app_vec_t ila_func_app
a collection of all function application
Definition: verilog_gen.h:281
ilang::VerilogGeneratorBase::cfg_
const VlgGenConfig cfg_
The configuration.
Definition: verilog_gen.h:313
ilang::VerilogGeneratorBase::wires
vlg_sigs_map_t wires
vector of wires to be defined
Definition: verilog_gen.h:236
ilang::VerilogGeneratorBase::TestVerilogExport
friend class TestVerilogExport
let the test class use this module
Definition: verilog_gen.h:41
ilang::VerilogGeneratorBase::clkName
vlg_name_t clkName
Clock signal name.
Definition: verilog_gen.h:204
ilang::VerilogGeneratorBase::check_reserved_name
bool check_reserved_name(const vlg_name_t &n) const
Check if a name is reserved (clk/rst/modulename/decodeName/ctrName)
ilang::VerilogGeneratorBase::init_stmts
vlg_stmts_t init_stmts
Definition: verilog_gen.h:247
ilang::VerilogGeneratorBase::IlaBvValUnsignedType
BvVal::BvValType IlaBvValUnsignedType
The unsigned type of bitvector value in ila.
Definition: verilog_gen.h:39
ilang::VerilogGeneratorBase::past_writes
mem_write_list_t past_writes
Definition: verilog_gen.h:271
ilang
ilang::VerilogGeneratorBase::vlg_sigs_map_t
std::map< vlg_name_t, int > vlg_sigs_map_t
Type of Verilog signals (a vector)
Definition: verilog_gen.h:85
ilang::VerilogGeneratorBase::function_app_t::func_name
const std::string func_name
ila func name
Definition: verilog_gen.h:123
ilang::VerilogGeneratorBase::add_external_mem
void add_external_mem(const vlg_name_t &mem_name, int addr_width, int data_width, int entry_num)
record an external memory
ilang::VerilogGeneratorBase::wires_keep
vlg_sig_keep_t wires_keep
a map to store if a wire needs to keep
Definition: verilog_gen.h:238
ilang::VerilogGeneratorBase::wport_t
type of write port
Definition: verilog_gen.h:57
ilang::VerilogGeneratorBase::ExprMap
std::unordered_map< const ExprPtr, vlg_name_t, VerilogGenHash > ExprMap
Type for caching the generated expressions.
Definition: verilog_gen.h:140
ilang::BvVal::BvValType
uint64_t BvValType
Data type for storing BvVal. NOTE: SHOULD BE SYNCED WITH NumericType!!
Definition: sort_value.h:71
ilang::VerilogGeneratorBase::ila_wports
std::map< std::string, std::map< unsigned, wport_t > > ila_wports
ila write ports
Definition: verilog_gen.h:279
ilang::VerilogGeneratorBase::state_update_ite_unknown
state_update_ite_unknown_map_t state_update_ite_unknown
a collection of all state update ite unknown
Definition: verilog_gen.h:283
ilang::VerilogGeneratorBase::vlg_ite_stmts_t
std::vector< vlg_ite_stmt_t > vlg_ite_stmts_t
Type of Verilog ITEs statements.
Definition: verilog_gen.h:93
ilang::VerilogGeneratorBase::vlg_stmt_t
std::string vlg_stmt_t
Type of Verilog statement.
Definition: verilog_gen.h:69
ilang::VerilogGeneratorBase::function_app_t::args
std::vector< vlg_sig_t > args
arguments
Definition: verilog_gen.h:119
ilang::VerilogGeneratorBase::IlaBvValType
BvVal::BvValType IlaBvValType
The type of bitvector value in ila.
Definition: verilog_gen.h:37
ilang::InstrLvlAbsPtr
InstrLvlAbs::InstrLvlAbsPtr InstrLvlAbsPtr
Pointer type for normal use of InstrLvlAbs.
Definition: instr_lvl_abs.h:326
ilang::VerilogGeneratorBase::reference_name_set
std::map< std::string, std::string > reference_name_set
reference name list
Definition: verilog_gen.h:315
ilang::VerilogGeneratorBase::function_app_t::function_app_t
function_app_t(const vlg_sig_t &res, const std::string fn)
constructor
Definition: verilog_gen.h:125
ilang::VerilogGeneratorBase::rport_t::ren
std::string ren
what to connect for ren
Definition: verilog_gen.h:54
ilang::VerilogGeneratorBase::state_update_unknown::condition
const vlg_name_t condition
the condition
Definition: verilog_gen.h:133
ilang::VerilogGeneratorBase::VlgGenConfig::VlgGenConfig
VlgGenConfig(bool ExternalMem=true, funcOption funcOpt=funcOption::Internal, bool gen_start=false, bool pass_name=false, bool rand_init=false, bool ExpandMem=false, bool CollectIteUnknownUpdate=false)
Definition: verilog_gen.h:170
ilang::VerilogGeneratorBase::AnnotateMemory
void AnnotateMemory(const memory_export_annotation_t &annotation)
add memory annotation, please invoke right after constructor
ilang::VerilogGeneratorBase::counterName
vlg_name_t counterName
The name of internal counter.
Definition: verilog_gen.h:224
ilang::VerilogGeneratorBase::function_app_t
Type of app func.
Definition: verilog_gen.h:117
ilang::VerilogGeneratorBase::moduleName
vlg_name_t moduleName
Verilog Module Name.
Definition: verilog_gen.h:202
ilang::VerilogGeneratorBase::vlg_sig_t
std::pair< vlg_name_t, int > vlg_sig_t
Type of Verilog signal, name & bw.
Definition: verilog_gen.h:81
ilang::VerilogGeneratorBase::inputs
vlg_sigs_map_t inputs
vector of input signals
Definition: verilog_gen.h:226
ilang::VerilogGeneratorBase::preheader
vlg_stmt_t preheader
For auxiliary definitions.
Definition: verilog_gen.h:260
ilang::VerilogGeneratorBase::vlg_names_t
std::vector< vlg_name_t > vlg_names_t
Type of Verilog names (a vector)
Definition: verilog_gen.h:79
ilang::VerilogGeneratorBase::add_input
void add_input(const vlg_name_t &n, int w)
record an input signal
ilang::VerilogGeneratorBase::outputs
vlg_sigs_map_t outputs
vector of output signals
Definition: verilog_gen.h:228
ilang::VerilogGeneratorBase::wport_t::wen
std::string wen
what to connect for wen
Definition: verilog_gen.h:63
ilang::VerilogGeneratorBase::decodeNames
vlg_names_t decodeNames
Definition: verilog_gen.h:209
ilang::VerilogGeneratorBase::add_init_stmt
void add_init_stmt(const vlg_stmt_t &s)
record an assignemnt in the always block (in if(rst) branch )
ilang::VerilogGenerator::VerilogGenerator
VerilogGenerator(const VlgGenConfig &config=VlgGenConfig(), const std::string &modName="", const std::string &clk="clk", const std::string &rst="rst")
ilang::VerilogGeneratorBase::always_stmts
vlg_stmts_t always_stmts
statements to be used in the always block but out of the reset
Definition: verilog_gen.h:254
ilang::VerilogGeneratorBase::new_id
vlg_name_t new_id()
get a new id
ilang::InstrPtr
Instr::InstrPtr InstrPtr
Pointer type for normal use of Instr.
Definition: instr.h:138
ilang::VerilogGeneratorBase::VlgGenConfig::extMem
bool extMem
Definition: verilog_gen.h:153
ilang::VerilogGeneratorBase::VlgGenConfig::pass_node_name
bool pass_node_name
whether to set vlg name according to the node name
Definition: verilog_gen.h:159
ilang::VerilogGeneratorBase::rport_t
type of read port
Definition: verilog_gen.h:48
ilang::VerilogGeneratorBase::get_width
static int get_width(const ExprPtr &n)
Get the width of an ExprPtr, must be supported sort.
ilang::VerilogGeneratorBase::init_assumpts
vlg_stmts_t init_assumpts
Definition: verilog_gen.h:250
ilang::VerilogGeneratorBase::ToVlgNum
static vlg_const_t ToVlgNum(IlaBvValType value, unsigned width)
will force to be hex
instr_lvl_abs.h
ilang::VerilogGeneratorBase::wport_t::wdata
std::string wdata
what to connect for wdata
Definition: verilog_gen.h:61
ilang::VerilogGeneratorBase::add_output
void add_output(const vlg_name_t &n, int w)
record an output signal
ilang::VerilogGeneratorBase::mem_write_t
This is the write and its associated condition.
Definition: verilog_gen.h:109
ilang::VerilogGeneratorBase::vlg_sigs_set_t
std::set< vlg_sig_t > vlg_sigs_set_t
Type of set of Verilog signals.
Definition: verilog_gen.h:89
ilang::VerilogGenerator::vlg_name_t
VerilogGeneratorBase::vlg_name_t vlg_name_t
Type of Verilog id names'.
Definition: verilog_gen.h:379
ilang::VerilogGeneratorBase::add_preheader
void add_preheader(const vlg_stmt_t &stmt)
add an item to the preheader
ilang::VerilogGeneratorBase::memory_export_annotation_t
std::map< std::string, bool > memory_export_annotation_t
Type for memory annotation.
Definition: verilog_gen.h:145
ilang::VerilogGenerator
Class of Verilog Generator.
Definition: verilog_gen.h:373
ilang::VerilogGeneratorBase::grantAccName
vlg_sig_t grantAccName
Definition: verilog_gen.h:220
ilang::VerilogGeneratorBase::add_reg
void add_reg(const vlg_name_t &n, int w)
record a register
ilang::VerilogGeneratorBase::function_app_t::result
const vlg_sig_t result
result
Definition: verilog_gen.h:121
ilang::VerilogGeneratorBase::VlgGenConfig::VlgGenConfig
VlgGenConfig(const VlgGenConfig &c, bool ExternalMem, funcOption funcOpt, bool gen_start, bool rand_init, bool ExpandMem, bool CollectIteUnknownUpdate)
Overwrite configuration, used by vtarget gen.
Definition: verilog_gen.h:178