ilang  0.9.1
ILAng: A Modeling and Verification Platform for SoCs
Public Member Functions | Protected Member Functions | Protected Attributes | List of all members
ilang::VlgVerifTgtGen Class Reference

#include <vtarget_gen_impl.h>

Inheritance diagram for ilang::VlgVerifTgtGen:
ilang::VlgVerifTgtGenBase

Public Member Functions

 VlgVerifTgtGen (const std::vector< std::string > &implementation_include_path, const std::vector< std::string > &implementation_srcs, const std::string &implementation_top_module, const std::string &refinement_variable_mapping, const std::string &refinement_conditions, const std::string &output_path, const InstrLvlAbsPtr &ila_ptr, backend_selector backend, const vtg_config_t &vtg_config, const VerilogGenerator::VlgGenConfig &config=VerilogGenerator::VlgGenConfig())
 
 VlgVerifTgtGen (const VlgVerifTgtGen &)=delete
 no copy constructor, please
 
VlgVerifTgtGenoperator= (const VlgVerifTgtGen &)=delete
 no assignment, please. I don't want to mess up w. vlg_info_ptr
 
virtual ~VlgVerifTgtGen ()
 release verilog info pointer
 
void GenerateTargets (void)
 Generate everything.
 
bool in_bad_state (void) const
 Return true if it is in bad state.
 

Protected Member Functions

bool bad_state_return (void)
 If it is bad state, return true and display a message.
 
void load_json (const std::string &fname, nlohmann::json &j)
 load json from a file name to the given j
 
void set_module_instantiation_name ()
 Get instance name from rfmap.
 

Protected Attributes

const std::vector< std::string > _vlg_impl_include_path
 implementation include path
 
const std::vector< std::string > _vlg_impl_srcs
 implementatino path
 
const std::string _vlg_impl_top_name
 implementation top module name
 
const std::string _rf_var_map_name
 refinement relation - variable mapping path
 
const std::string _rf_cond_name
 refinement relation - condition path
 
const std::string _output_path
 
const InstrLvlAbsPtr_ila_ptr
 The pointer to the instruction that is going to export.
 
std::string _vlg_mod_inst_name
 The name of verilog top module instance in the wrapper.
 
std::string _ila_mod_inst_name
 The name of ila-verilog top module instance in the wrapper.
 
VerilogInfovlg_info_ptr
 A pointer to create verilog analyzer.
 
backend_selector _backend
 to store the backend
 
VerilogGenerator::VlgGenConfig _cfg
 to store the verilog configuration
 
vtg_config_t _vtg_config
 to store the configuration
 
nlohmann::json rf_vmap
 store the vmap info
 
nlohmann::json rf_cond
 store the condition
 

Additional Inherited Members

- Public Types inherited from ilang::VlgVerifTgtGenBase
enum  backend_selector { NONE = 0, COSA = 1, JASPERGOLD = 2 }
 Type of the backend.
 
typedef struct ilang::VlgVerifTgtGenBase::_vtg_config vtg_config_t
 Verilog Target Generation Configuration.
 

Detailed Description

brief Class of Verilog verification target generation, not to be used outside

Constructor & Destructor Documentation

◆ VlgVerifTgtGen()

ilang::VlgVerifTgtGen::VlgVerifTgtGen ( const std::vector< std::string > &  implementation_include_path,
const std::vector< std::string > &  implementation_srcs,
const std::string &  implementation_top_module,
const std::string &  refinement_variable_mapping,
const std::string &  refinement_conditions,
const std::string &  output_path,
const InstrLvlAbsPtr ila_ptr,
backend_selector  backend,
const vtg_config_t vtg_config,
const VerilogGenerator::VlgGenConfig config = VerilogGenerator::VlgGenConfig() 
)
Parameters
[in]implementation'sinclude path (if it uses `include)
[in]verilog'spath, currently we only handle situation where all in the same folder
[in]nameof the top module of the implementation, leave "" to allow auto analysis
[in]whereto get variable mapping
[in]whereto get refinement relation
[in]outputpath (ila-verilog, wrapper-verilog, problem.txt, run-verify-by-???, modify-impl, it there is )
[in]pointerto the ila
[in](optional)the default configuration for outputing verilog

Member Data Documentation

◆ _output_path

const std::string ilang::VlgVerifTgtGen::_output_path
protected

output path, output the ila-verilog, wrapper-verilog, problem.txt, run-verify-by-???


The documentation for this class was generated from the following file: