ilang  1.0.2
ILAng: A Modeling and Verification Platform for SoCs
Public Types | Public Member Functions | List of all members
ilang::VerilogVerificationTargetGenerator Class Reference

Public Types

using backend_selector = VlgVerifTgtGenBase::backend_selector
 Type of the backend.
using synthesis_backend_selector = VlgVerifTgtGenBase::synthesis_backend_selector
 Type of the synthesis backend.
using vtg_config_t = VlgVerifTgtGenBase::vtg_config_t
 Type of configuration.

Public Member Functions

 VerilogVerificationTargetGenerator (const std::vector< std::string > &implementation_include_path, const std::vector< std::string > &implementation_srcs, const std::string &implementation_top_module, const std::string &refinement_variable_mapping, const std::string &refinement_conditions, const std::string &output_path, const InstrLvlAbsPtr &ila_ptr, backend_selector backend, const vtg_config_t &vtg_config=vtg_config_t(), const VerilogGenerator::VlgGenConfig &config=VerilogGenerator::VlgGenConfig())
void GenerateTargets (void)
 export all targets
bool in_bad_state (void) const
 return true if the generator's in a bad state and cannot proceed.
std::string GetVlgModuleInstanceName (void) const
 get vlg-module instance name

Constructor & Destructor Documentation

◆ VerilogVerificationTargetGenerator()

ilang::VerilogVerificationTargetGenerator::VerilogVerificationTargetGenerator ( const std::vector< std::string > &  implementation_include_path,
const std::vector< std::string > &  implementation_srcs,
const std::string &  implementation_top_module,
const std::string &  refinement_variable_mapping,
const std::string &  refinement_conditions,
const std::string &  output_path,
const InstrLvlAbsPtr ila_ptr,
backend_selector  backend,
const vtg_config_t vtg_config = vtg_config_t(),
const VerilogGenerator::VlgGenConfig config = VerilogGenerator::VlgGenConfig() 
[in]implementation'sinclude path (if it uses `include)
[in]verilog'spath, currently we only handle situation where all in the same folder
[in]nameof the top module of the implementation, leave "" to allow auto analysis
[in]whereto get variable mapping
[in]whereto get refinement relation
[in]outputpath (ila-verilog, wrapper-verilog, problem.txt, run-verify-by-???, modify-impl, it there is )
[in]pointerto the ila
[in]thebackend selector
[in](optional)the default configuration for outputing verilog

The documentation for this class was generated from the following file: