ilang  1.0.2
ILAng: A Modeling and Verification Platform for SoCs
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ilang::VerilogInfo Class Reference

The class that invoke the analyzer. More...

#include <verilog_analysis_wrapper.h>

Public Types

using path_vec_t = VerilogAnalyzerBase::path_vec_t
 type to store multiple paths
using vlg_loc_t = VerilogAnalyzerBase::vlg_loc_t
 filename, line number pair : location type
using name_names_map_t = VerilogAnalyzerBase::name_names_map_t
 A map of name -> names.
using mod_inst_t = VerilogAnalyzerBase::mod_inst_t
 type of modulename instance name : instance_name->module_name
using name_insts_map_t = VerilogAnalyzerBase::name_insts_map_t
 A map of module name -> instantiation.
using hierarchical_name_type = VerilogAnalyzerBase::hierarchical_name_type
 The result of querying a name (please don't change the order of them)
using name_type_buffer_t = VerilogAnalyzerBase::name_type_buffer_t
 hierarchical name -> hierarchical_name_type map
using name_decl_buffer_t = VerilogAnalyzerBase::name_decl_buffer_t
 hierarchical name -> declaration pointer
using module_io_vec_t = VerilogAnalyzerBase::module_io_vec_t
 Top module signal list.

Public Member Functions

 VerilogInfo (const path_vec_t &include_path, const path_vec_t &srcs, const std::string &top_module_inst_name, const std::string &optional_top_module="")
 VerilogInfo (const VerilogInfo &)=delete
 Please don't make a copy of it.
VerilogInfooperator= (const VerilogInfo &)=delete
 Please don't use assignment over it.
virtual ~VerilogInfo ()
 Destructor: no need to clean, unique_ptr does the job.
hierarchical_name_type check_hierarchical_name_type (const std::string &net_name) const
 Return the type of a name (used externally, cached)
void * find_declaration_of_name (const std::string &net_name) const
vlg_loc_t name2loc (const std::string &net_name) const
 Return the location of a hierarchical name.
vlg_loc_t get_module_inst_loc (const std::string &inst_name) const
 Return the location of a module instantiation.
vlg_loc_t get_endmodule_loc (const std::string &inst_name) const
 Return the location of a module's endmodule statement.
std::string get_top_module_name () const
 Return top module name.
module_io_vec_t get_top_module_io () const
 Return top module signal with no hint on the width.
module_io_vec_t get_top_module_io (const std::map< std::string, int > &width_info) const
 Return top module signal.
SignalInfoBase get_signal (const std::string &net_name) const
 Find a signal.
SignalInfoBase get_signal (const std::string &net_name, const std::map< std::string, int > &width_info) const
 Find a signal (and use the width info, if width is unknown)
bool in_bad_state () const
 whether this analyzer is in bad state

Detailed Description

The class that invoke the analyzer.

Constructor & Destructor Documentation

◆ VerilogInfo()

ilang::VerilogInfo::VerilogInfo ( const path_vec_t include_path,
const path_vec_t srcs,
const std::string &  top_module_inst_name,
const std::string &  optional_top_module = "" 

Analyze a set of file [in] the path to search for include [in] the source files [in] the instance name given to the topmodule

[in]anoptional of the top module name, can be left empty

Member Function Documentation

◆ find_declaration_of_name()

void* ilang::VerilogInfo::find_declaration_of_name ( const std::string &  net_name) const

Return the declaration of a name, which could be be converted to: ast_module_declaration, ast_net_declaration, ast_reg_declaration, ast_port_declaration (should not be used!) because you don't know what to convert left here for debugging purpose only

The documentation for this class was generated from the following file: