ilang  0.9.1
ILAng: A Modeling and Verification Platform for SoCs
Public Types | Public Member Functions | Friends | List of all members
ilang::VerilogGenerator Class Reference

Class of Verilog Generator. More...

#include <verilog_gen.h>

Inheritance diagram for ilang::VerilogGenerator:
ilang::VerilogGeneratorBase

Public Types

using vlg_name_t = VerilogGeneratorBase::vlg_name_t
 Type of Verilog id names'.
 
using vlg_stmt_t = VerilogGeneratorBase::vlg_stmt_t
 Type of Verilog statement.
 
using vlg_addr_t = VerilogGeneratorBase::vlg_addr_t
 Type of Verilog address.
 
using vlg_data_t = VerilogGeneratorBase::vlg_data_t
 Type of Verilog data.
 
using vlg_stmts_t = VerilogGeneratorBase::vlg_stmts_t
 Type of Verilog statements (a vector)
 
using vlg_names_t = VerilogGeneratorBase::vlg_names_t
 Type of Verilog names (a vector)
 
using vlg_sig_t = VerilogGeneratorBase::vlg_sig_t
 Type of Verilog signal, name & bw.
 
using vlg_sigs_t = VerilogGeneratorBase::vlg_sigs_t
 Type of Verilog signals (a vector)
 
using vlg_sig_keep_t = VerilogGeneratorBase::vlg_sig_keep_t
 Type of a map: name -> need to add keep?
 
using vlg_sigs_set_t = VerilogGeneratorBase::vlg_sigs_set_t
 Type of set of Verilog signals.
 
using vlg_ite_stmt_t = VerilogGeneratorBase::vlg_ite_stmt_t
 Type of Verilog ITEs (IN sequential block)
 
using vlg_ite_stmts_t = VerilogGeneratorBase::vlg_ite_stmts_t
 Type of Verilog ITEs statements.
 
using vlg_mem_t = VerilogGeneratorBase::vlg_mem_t
 Type of the memorys that are going to be created.
 
using vlg_mems_rec_t = VerilogGeneratorBase::vlg_mems_rec_t
 Type of collection of memorys.
 
using mem_write_entry_t = VerilogGeneratorBase::mem_write_entry_t
 This is type of an individual write.
 
using mem_write_entry_list_t = VerilogGeneratorBase::mem_write_entry_list_t
 This is type of a list of writes.
 
using mem_write_entry_list_stack_t = VerilogGeneratorBase::mem_write_entry_list_stack_t
 Type of a stack of writes use in visitMemNodes.
 
using mem_write_t = VerilogGeneratorBase::mem_write_t
 This is the write and its associated condition.
 
using mem_write_list_t = VerilogGeneratorBase::mem_write_list_t
 List of writes w. associated conditions.
 
using ExprMap = VerilogGeneratorBase::ExprMap
 Type for caching the generated expressions.
 
using VlgGenConfig = VerilogGeneratorBase::VlgGenConfig
 the structure to configure the verilog generator
 
using function_app_t = VerilogGeneratorBase::function_app_t
 Type of function apply record.
 
using function_app_vec_t = VerilogGeneratorBase::function_app_vec_t
 Type of func app vector record.
 
- Public Types inherited from ilang::VerilogGeneratorBase
typedef std::string vlg_name_t
 Type of Verilog id names.
 
typedef std::string vlg_stmt_t
 Type of Verilog statement.
 
typedef std::string vlg_addr_t
 Type of Verilog address.
 
typedef std::string vlg_data_t
 Type of Verilog data.
 
typedef std::vector< vlg_name_tvlg_stmts_t
 Type of Verilog statements (a vector)
 
typedef std::vector< vlg_name_tvlg_names_t
 Type of Verilog names (a vector)
 
typedef std::pair< vlg_name_t, int > vlg_sig_t
 Type of Verilog signal, name & bw.
 
typedef std::vector< vlg_sig_tvlg_sigs_t
 Type of Verilog signals (a vector)
 
typedef std::map< vlg_name_t, int > vlg_sigs_map_t
 Type of Verilog signals (a vector)
 
typedef std::map< vlg_name_t, bool > vlg_sig_keep_t
 Type of a map: name -> need to add keep?
 
typedef std::set< vlg_sig_tvlg_sigs_set_t
 Type of set of Verilog signals.
 
typedef std::tuple< vlg_stmt_t, vlg_stmt_t, vlg_stmt_tvlg_ite_stmt_t
 Type of Verilog ITEs (IN sequential block)
 
typedef std::vector< vlg_ite_stmt_tvlg_ite_stmts_t
 Type of Verilog ITEs statements.
 
typedef std::tuple< vlg_name_t, int, int > vlg_mem_t
 Type of the memorys that are going to be created.
 
typedef std::map< vlg_name_t, vlg_mem_tvlg_mems_rec_t
 Type of collection of memorys.
 
typedef std::list< mem_write_entry_tmem_write_entry_list_t
 This is type of a list of writes.
 
typedef std::list< mem_write_entry_list_tmem_write_entry_list_stack_t
 Type of a stack of writes use in visitMemNodes.
 
typedef std::list< mem_write_tmem_write_list_t
 List of writes w. associated conditions.
 
typedef std::vector< function_app_tfunction_app_vec_t
 
typedef std::unordered_map< const ExprPtr, vlg_name_t, VerilogGenHashExprMap
 Type for caching the generated expressions.
 

Public Member Functions

 VerilogGenerator (const VlgGenConfig &config=VlgGenConfig(), const std::string &modName="", const std::string &clk="clk", const std::string &rst="rst")
 
void ExportIla (const InstrLvlAbsPtr &ila_ptr_)
 Parse an ILA, will gen all its instructions.
 
void ExportTopLevelInstr (const InstrPtr &instr_ptr_)
 Parse an instruction.
 
- Public Member Functions inherited from ilang::VerilogGeneratorBase
void add_input (const vlg_name_t &n, int w)
 record an input signal
 
void add_output (const vlg_name_t &n, int w)
 record an output signal
 
void add_wire (const vlg_name_t &n, int w, bool keep=false)
 record a wire
 
void add_reg (const vlg_name_t &n, int w)
 record a register
 
void add_stmt (const vlg_stmt_t &s)
 record a stmt (outside the always block)
 
void add_assign_stmt (const vlg_name_t &l, const vlg_name_t &r)
 record an assignment stmt (outside the always block), will call add_stmt
 
void add_always_stmt (const vlg_stmt_t &s)
 
void add_init_stmt (const vlg_stmt_t &s)
 record an assignemnt in the always block (in if(rst) branch )
 
void add_ite_stmt (const vlg_stmt_t &cond, const vlg_stmt_t &tstmt, const vlg_stmt_t &fstmt)
 
void add_internal_mem (const vlg_name_t &mem_name, int addr_width, int data_width)
 record an internal memory
 
void add_external_mem (const vlg_name_t &mem_name, int addr_width, int data_width)
 record an external memory
 
void add_preheader (const vlg_stmt_t &stmt)
 add an item to the preheader
 
 VerilogGeneratorBase (const VlgGenConfig &config=VlgGenConfig(), const std::string &modName="", const std::string &clk="clk", const std::string &rst="rst")
 
virtual void DumpToFile (std::ostream &fout) const
 

Friends

class TestVerilogExport
 let the test class use this module
 

Additional Inherited Members

- Static Public Member Functions inherited from ilang::VerilogGeneratorBase
static vlg_name_t sanitizeName (const vlg_name_t &n)
 sanitize a name string, so it will generate illegal verilog identifier
 
static vlg_name_t sanitizeName (const ExprPtr &n)
 
- Protected Member Functions inherited from ilang::VerilogGeneratorBase
bool check_reserved_name (const vlg_name_t &n) const
 Check if a name is reserved (clk/rst/modulename/decodeName/ctrName)
 
vlg_name_t new_id ()
 get a new id
 
vlg_name_t new_id (const ExprPtr &e)
 
- Static Protected Member Functions inherited from ilang::VerilogGeneratorBase
static int get_width (const ExprPtr &n)
 Get the width of an ExprPtr, must be supported sort.
 
static std::string WidthToRange (int w)
 convert a widith to a verilog string
 
- Protected Attributes inherited from ilang::VerilogGeneratorBase
vlg_name_t moduleName
 Verilog Module Name.
 
vlg_name_t clkName
 Clock signal name.
 
vlg_name_t rstName
 Reset signal name.
 
vlg_names_t decodeNames
 
vlg_name_t validName
 
vlg_name_t startName
 start signal name, may not be used
 
vlg_sig_t grantAccName
 
vlg_sig_t decodeAccName
 accumulated decode signals
 
vlg_name_t counterName
 The name of internal counter.
 
vlg_sigs_map_t inputs
 vector of input signals
 
vlg_sigs_map_t outputs
 vector of output signals
 
vlg_sigs_t mem_i
 vector of memory input signals
 
vlg_sigs_t mem_o
 vector of memory output signals
 
vlg_sigs_map_t wires
 vector of wires to be defined
 
vlg_sig_keep_t wires_keep
 a map to store if a wire needs to keep
 
vlg_sigs_t regs
 vector of regs to be defined
 
vlg_mems_rec_t mems_internal
 vector of mems to be defined
 
vlg_mems_rec_t mems_external
 vector of mems from outside (will not be defined)
 
vlg_stmts_t init_stmts
 
vlg_stmts_t init_assumpts
 
vlg_stmts_t statements
 statements to be outside the always block
 
vlg_stmts_t always_stmts
 statements to be used in the always block but out of the reset
 
vlg_ite_stmts_t ite_stmts
 
vlg_stmt_t preheader
 For auxiliary definitions.
 
ExprMap nmap
 The map to cache the expression (we only need to store the name)
 
mem_write_list_t current_writes
 For traverse a mem expression.
 
mem_write_list_t past_writes
 
vlg_sigs_set_t all_valid_names
 to hold all valid names, a sanity check
 
std::map< std::string, std::map< unsigned, rport_t > > ila_rports
 
std::map< std::string, std::map< unsigned, wport_t > > ila_wports
 ila write ports
 
function_app_vec_t ila_func_app
 a collection of all function application
 
unsigned idCounter
 The id counter.
 
const VlgGenConfig cfg_
 The configuration.
 
std::map< std::string, std::string > reference_name_set
 reference name list
 
std::set< FuncPtrfunc_ptr_set
 

Detailed Description

Class of Verilog Generator.

Constructor & Destructor Documentation

◆ VerilogGenerator()

ilang::VerilogGenerator::VerilogGenerator ( const VlgGenConfig config = VlgGenConfig(),
const std::string &  modName = "",
const std::string &  clk = "clk",
const std::string &  rst = "rst" 
)
Parameters
[in]Configuration
[in]Topmodule name, if empty, get it from instruction name
[in]clocksignal name
[in]resetsignal name

The documentation for this class was generated from the following file: