ilang  1.0.2
ILAng: A Modeling and Verification Platform for SoCs
ilang::VerilogGenerator Member List

This is the complete list of members for ilang::VerilogGenerator, including all inherited members.

add_always_stmt(const vlg_stmt_t &s)ilang::VerilogGeneratorBase
add_assign_stmt(const vlg_name_t &l, const vlg_name_t &r)ilang::VerilogGeneratorBase
add_external_mem(const vlg_name_t &mem_name, int addr_width, int data_width, int entry_num)ilang::VerilogGeneratorBase
add_init_stmt(const vlg_stmt_t &s)ilang::VerilogGeneratorBase
add_input(const vlg_name_t &n, int w)ilang::VerilogGeneratorBase
add_internal_mem(const vlg_name_t &mem_name, int addr_width, int data_width, int entry_num)ilang::VerilogGeneratorBase
add_ite_stmt(const vlg_stmt_t &cond, const vlg_stmt_t &tstmt, const vlg_stmt_t &fstmt)ilang::VerilogGeneratorBase
add_output(const vlg_name_t &n, int w)ilang::VerilogGeneratorBase
add_preheader(const vlg_stmt_t &stmt)ilang::VerilogGeneratorBase
add_reg(const vlg_name_t &n, int w)ilang::VerilogGeneratorBase
add_stmt(const vlg_stmt_t &s)ilang::VerilogGeneratorBase
add_wire(const vlg_name_t &n, int w, bool keep=false)ilang::VerilogGeneratorBase
all_valid_namesilang::VerilogGeneratorBaseprotected
always_stmtsilang::VerilogGeneratorBaseprotected
AnnotateMemory(const memory_export_annotation_t &annotation)ilang::VerilogGeneratorBase
cfg_ilang::VerilogGeneratorBaseprotected
check_reserved_name(const vlg_name_t &n) constilang::VerilogGeneratorBaseprotected
clkNameilang::VerilogGeneratorBaseprotected
cmapilang::VerilogGeneratorBaseprotected
CnstMap typedefilang::VerilogGeneratorBase
counterNameilang::VerilogGeneratorBaseprotected
current_writesilang::VerilogGeneratorBaseprotected
decodeAccNameilang::VerilogGeneratorBaseprotected
decodeNamesilang::VerilogGeneratorBaseprotected
DumpToFile(std::ostream &fout) constilang::VerilogGeneratorBasevirtual
ExportIla(const InstrLvlAbsPtr &ila_ptr_)ilang::VerilogGenerator
ExportTopLevelInstr(const InstrPtr &instr_ptr_)ilang::VerilogGenerator
ExprMap typedefilang::VerilogGenerator
func_ptr_setilang::VerilogGeneratorBaseprotected
function_app_t typedefilang::VerilogGenerator
function_app_vec_t typedefilang::VerilogGenerator
get_width(const ExprPtr &n)ilang::VerilogGeneratorBaseprotectedstatic
grantAccNameilang::VerilogGeneratorBaseprotected
idCounterilang::VerilogGeneratorBaseprotected
ila_func_appilang::VerilogGeneratorBaseprotected
ila_rportsilang::VerilogGeneratorBaseprotected
ila_wportsilang::VerilogGeneratorBaseprotected
IlaBoolValType typedefilang::VerilogGeneratorBase
IlaBvValType typedefilang::VerilogGeneratorBase
IlaBvValUnsignedType typedefilang::VerilogGeneratorBase
init_assumptsilang::VerilogGeneratorBaseprotected
init_stmtsilang::VerilogGeneratorBaseprotected
inputsilang::VerilogGeneratorBaseprotected
ite_stmtsilang::VerilogGeneratorBaseprotected
mem_iilang::VerilogGeneratorBaseprotected
mem_oilang::VerilogGeneratorBaseprotected
mem_probe_oilang::VerilogGeneratorBaseprotected
mem_write_entry_list_stack_t typedefilang::VerilogGenerator
mem_write_entry_list_t typedefilang::VerilogGenerator
mem_write_entry_t typedefilang::VerilogGenerator
mem_write_list_t typedefilang::VerilogGenerator
mem_write_t typedefilang::VerilogGenerator
memory_export_annotation (defined in ilang::VerilogGeneratorBase)ilang::VerilogGeneratorBaseprotected
memory_export_annotation_t typedefilang::VerilogGeneratorBase
mems_externalilang::VerilogGeneratorBaseprotected
mems_internalilang::VerilogGeneratorBaseprotected
moduleNameilang::VerilogGeneratorBaseprotected
new_id()ilang::VerilogGeneratorBaseprotected
new_id(const ExprPtr &e)ilang::VerilogGeneratorBaseprotected
nmapilang::VerilogGeneratorBaseprotected
outputsilang::VerilogGeneratorBaseprotected
past_writesilang::VerilogGeneratorBaseprotected
preheaderilang::VerilogGeneratorBaseprotected
reference_name_setilang::VerilogGeneratorBaseprotected
regsilang::VerilogGeneratorBaseprotected
rstNameilang::VerilogGeneratorBaseprotected
sanitizeName(const vlg_name_t &n)ilang::VerilogGeneratorBasestatic
sanitizeName(const ExprPtr &n)ilang::VerilogGeneratorBasestatic
startNameilang::VerilogGeneratorBaseprotected
state_update_ite_unknownilang::VerilogGeneratorBaseprotected
state_update_ite_unknown_map_t typedef (defined in ilang::VerilogGeneratorBase)ilang::VerilogGeneratorBase
statementsilang::VerilogGeneratorBaseprotected
TestVerilogExport classilang::VerilogGeneratorfriend
ToVlgNum(IlaBvValType value, unsigned width)ilang::VerilogGeneratorBasestatic
validNameilang::VerilogGeneratorBaseprotected
VerilogGenerator(const VlgGenConfig &config=VlgGenConfig(), const std::string &modName="", const std::string &clk="clk", const std::string &rst="rst")ilang::VerilogGenerator
VerilogGeneratorBase(const VlgGenConfig &config=VlgGenConfig(), const std::string &modName="", const std::string &clk="clk", const std::string &rst="rst")ilang::VerilogGeneratorBase
vlg_addr_t typedefilang::VerilogGenerator
vlg_const_t typedefilang::VerilogGeneratorBase
vlg_data_t typedefilang::VerilogGenerator
vlg_ite_stmt_t typedefilang::VerilogGenerator
vlg_ite_stmts_t typedefilang::VerilogGenerator
vlg_mem_t typedefilang::VerilogGenerator
vlg_mems_rec_t typedefilang::VerilogGenerator
vlg_name_t typedefilang::VerilogGenerator
vlg_names_t typedefilang::VerilogGenerator
vlg_sig_keep_t typedefilang::VerilogGenerator
vlg_sig_t typedefilang::VerilogGenerator
vlg_sigs_map_t typedefilang::VerilogGeneratorBase
vlg_sigs_set_t typedefilang::VerilogGenerator
vlg_sigs_t typedefilang::VerilogGenerator
vlg_stmt_t typedefilang::VerilogGenerator
vlg_stmts_t typedefilang::VerilogGenerator
VlgGenConfig typedefilang::VerilogGenerator
WidthToRange(int w)ilang::VerilogGeneratorBaseprotectedstatic
wiresilang::VerilogGeneratorBaseprotected
wires_keepilang::VerilogGeneratorBaseprotected