ilang  0.9.1
ILAng: A Modeling and Verification Platform for SoCs
Public Member Functions | Protected Attributes | List of all members
ilang::SignalInfoReg Class Reference

Class to convert reg to signal info. More...

#include <verilog_analysis.h>

Inheritance diagram for ilang::SignalInfoReg:
ilang::SignalInfoBase

Public Member Functions

 SignalInfoReg (ast_reg_declaration *def, const std::string &full_name, VerilogAnalyzerBase::hierarchical_name_type tp, ast_module_declaration *mod)
 
ast_reg_declaration * get_def ()
 Return its definition.
 
- Public Member Functions inherited from ilang::SignalInfoBase
virtual unsigned get_width () const
 
virtual bool is_io_sig () const
 Whether is a IO signal.
 
virtual bool no_internal_def () const
 Whether it is defined only at the port.
 
virtual bool is_reg () const
 Whether it is a register.
 
virtual bool is_input () const
 Whether it is an input signal.
 
virtual bool is_output () const
 Whether it is an output signal.
 
virtual bool is_bad_signal () const
 Whether this info is usable.
 
virtual VerilogAnalyzerBase::hierarchical_name_type get_type () const
 return its type
 
virtual VerilogAnalyzerBase::vlg_loc_t get_decl_loc () const
 Return its location.
 
virtual std::string get_signal_name () const
 Return is own name.
 
virtual std::string get_hierarchical_name () const
 Return its hierarchical name.
 
 SignalInfoBase (const std::string &n, const std::string &h, unsigned w, const VerilogAnalyzerBase::hierarchical_name_type &typ, const VerilogAnalyzerBase::vlg_loc_t &loc)
 ------------------— ACCESSORS ----------------— ///
 

Protected Attributes

ast_reg_declaration * _def
 Stores its own definition.
 
- Protected Attributes inherited from ilang::SignalInfoBase
const std::string _name
 
const std::string _hierarchical_name
 full name
 
const unsigned _width
 width of the signal
 
const VerilogAnalyzerBase::hierarchical_name_type _type
 its type
 
const VerilogAnalyzerBase::vlg_loc_t _loc
 its location of definition
 

Detailed Description

Class to convert reg to signal info.

Constructor & Destructor Documentation

◆ SignalInfoReg()

ilang::SignalInfoReg::SignalInfoReg ( ast_reg_declaration *  def,
const std::string &  full_name,
VerilogAnalyzerBase::hierarchical_name_type  tp,
ast_module_declaration *  mod 
)

Constructor: from ast_port_declaration – will parse the parameters of itself


The documentation for this class was generated from the following file: