I am a PhD candidate in the Department of Electrical Engineering at Princeton University working with Prof. Sharad Malik.
My research interest is applying formal methods in accelerator-rich computing platforms, especially software/hardware co-verification and co-synthesis.
I am also interested in security related system verification.
My current focus is instruction-level abstraction based SoC firmware synthesis.
Before coming to Princeton, I received my BS in Electrical Engineering from National Taiwan University.
- May, 2019. “Hardware/Software Interface for Heterogeneous Systems-on-Chip: @ ADA Annual Review
- Apr, 2019. “ILAng: A Modeling and Verification Platform for SoC using Instruction-Level Abstraction” @ TACAS
- Jan, 2019. “Formal specification for open-source hardware” @ DARPA POSH/IDEA Integration Meeting
- Nov, 2018. “Firmware Co-verification in Heterogeneous SoCs” @ ADA Liaison Meeting
- Sep, 2018. “Formal Security Verification of Concurrent Firmware in SocS using Instruction-Level Abstraction for Hardware” @ TechCon
- Jun, 2018. “Formal Security Verification of Concurrent Firmware in SocS using Instruction-Level Abstraction for Hardware” @ DAC
- May, 2018. “Formware Verification of Firmware in Heterogeneous SoCs” @ ADA
- Sep, 2017. “Democratizing Instructions: Instruction-Level Abstraction for SoC Designs and Verifications” @ CFAR
- Sep, 2017. “Instruction-Level Abstraction (ILA): Democratizing Instructions for SoCs” (Best in Session) @ TechCon
- May, 2017. “A Formal Model for Instruction-Level Abstraction of Hardware and its Application” @ Research Seminar, Princeton
- Dec, 2016. “Democratizing Instructions: Instruction-Level Abstraction for SoC Designs and Verifications” @ CFAR
- Oct, 2016. Student forum “Instruction-level abstraction based SoC firmware verification” @ FMCAD
- May, 2016. Our open-source instruction-level abstraction toolchain (ILA) is available.
- Apr, 2015. Awarded Francis Robbins Upton Fellowship
- ILAng: A Modeling and Verification Platform for SoCs using Instruction-Level Abstractions
Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, and Sharad Malik
International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), 2019
- A Formal Instruction-Level GPU Model for Scalable Verification
Yue Xing, Bo-Yuan Huang, Aarti Gupta, and Sharad Malik
International Conference on Computer-Aided Design (ICCAD), 2018
- Formal Security Verification of Concurrent Firmware in SoCs using Instruction-Level Abstraction for Hardware
Bo-Yuan Huang, Sayak Ray, Aarti Gupta, Jason Fung, and Sharad Malik
Design Automation Conference (DAC), 2018
- Asynchronous QDI Circuit Synthesis from Signal Transition Protocols
Bo-Yuan Huang, Yi-Hsiang Lai, and Jie-Hong Roland Jiang
IEEE International Conference on Computer Aided Design (ICCAD), 2015
- Resource Allocation in D2D Communication – A Game Theoretic Approach
Bo-Yuan Huang, Shih-Tang Su, Chih-Yu Wang, Che-Wei Teh, and Hung-Yu Wei
IEEE International Conference on Communications (ICC), 2014
- Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification
Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan, Yakir Vizel, Aarti Gupta, and Sharad Malik
ACM Transactions on Design Automation of Electronic Systems (TODAES), 2018
- Template-based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification
Pramod Subramanyan, Bo-Yuan Huang, Yakir Vizel, Aarti Gupta, and Sharad Malik
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018
- Protocol Design and Game Theoretic Solutions for Device-to-Device Radio Resource Allocation
Shih-Tang Su, Bo-Yuan Huang, Chih-Yu Wang, Che-Wei Teh, and Hung-Yu Wei
IEEE Transactions on Vehicular Technology (TVT), 2016
- Research Intern, Microsoft Research.
Jun 2018 - Sep 2018, Redmond, WA
White-box fuzzing for attacker-memory-safety in OS kernel packet/file parsers.
Kernel-aware memory checker and symbolic pointer reasoning.
- Security Research Intern, Intel Coporation
Jun 2017 - Sep 2017, Hillsboro, OR
Concurrent firmware verification with LLVM/Boogie-based software verification tools.
Exploiting security properties in inter-IPs communication in an industrial SoC design.
- Security Research Intern, Intel Coporation
Jun 2016 - Sep 2016, Hillsboro, OR
Research on ILA-based SoC firmware verification methodology.
Exploiting security properties in SoC secure-boot features.
- Design Automation Intern, TSMC
Jun 2013 - Sep 2013, Hsinchu, Taiwan
Develop EDA tools for Advanced Process Transferring Group.
Programming training for research-develop engineers
- Head Lab Instructor, ELE 206/COS 306 Contemporary Logic Design, Princeton University, Fall 2018
- Head Preceptor, ELE 206/COS 306 Contemporary Logic Design, Princeton University, Fall 2018
- Lab Instructor, ELE 206/COS 306 Contemporary Logic Design, Princeton University, Fall 2017
- Preceptor, ELE 206/COS 306 Contemporary Logic Design, Princeton University, Fall 2017
- Lab Instructor, ELE 206/COS 306 Contemporary Logic Design, Princeton University, Fall 2016
- Preceptor, ELE 206/COS 306 Contemporary Logic Design, Princeton University, Fall 2016
- Yueling Zhang
CS Department Visiting Student, Spring 2018
Advisor: Prof. Aarti Gupta
Hardware Description (Verilog) Generation for Instruction-Level Abstraction (ILA)
- David Gilhooley
EE Department Senior Thesis, Fall 2016 - Spring 2017
Advisor: Prof. Sharad Malik
Software/Hardware Co-Verification: Google Verified Boot Firmware with Trusted Platform Module
- ILAng: A modeling and verification platform for Systems-on-chip (SoCs)
- IMDb: An open-source database for ILA models
- ItSy: Templated-based synthesis engine for ILA
- Summer School on Formal Technique, 2018
- Best in Session Award, TechCon, 2017
- Summer School on Formal Verification, 2017
- Verification Mentoring Workshop, Computer-Aided Verification, 2016
- Francis Robbins Upton Fellowship, 2015
- First Prize in NTUEE Outstanding Undergraduate Independent Research, 2014
- Second Prize in TSMC Special Research Competition, 2014
- Ministry of Science and Technology Research Grant, 2013
- President’s Awards (NTU), 2011, 2012, 2013, 2014
- First Prize in TSMC Semiconductor Elite Program, 2012
- First Prize in Microsoft WP Platform Workshop Innovation Award, 2012