I am an Offensive Security Researcher at Intel Corp. My research interests are in the design automation and verification of software/hardware systems. Specifically, I am interested in security verification (e.g., model checking, static analysis, or fuzzing) and the synthesis and compilation problem in heterogeneous computing platforms. Before joining Intel, I received my B.S. from National Taiwan University and got my M.A. and Ph.D. from Princeton University under the supervision of Prof. Sharad Malik.


Publications

2021

  • Yu Zeng, Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, and Sharad Malik
    Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators. Part I: Determining Architectural State Variables
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2021
    [Article]

2020

  • Patrice Godefroid, Bo-Yuan Huang, and Marina Polishchuk
    Intelligent REST API Data Fuzzing
    ACM Joint European Software Engineering Conference and Symposium on the Foundations of Software Engineering (FSE), 2020
    [Article] [Code]

2019

  • Bo-Yuan Huang, Hongce Zhang, Pramod Subramanyan, Yakir Vizel, Aarti Gupta, and Sharad Malik
    Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification
    ACM Transactions on Design Automation of Electronic Systems (TODAES), Best Paper Award, 2019.
    [Article] [Code]

  • Bo-Yuan Huang, Hongce Zhang, Aarti Gupta, and Sharad Malik
    ILAng: A Modeling and Verification Platform for SoCs using Instruction-Level Abstractions
    International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), 2019
    [Article] [Code] [Website]

2018

  • Yue Xing, Bo-Yuan Huang, Aarti Gupta, and Sharad Malik
    A Formal Instruction-Level GPU Model for Scalable Verification
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018
    [Article]

  • Bo-Yuan Huang, Sayak Ray, Aarti Gupta, Jason Fung, and Sharad Malik
    Formal Security Verification of Concurrent Firmware in SoCs using Instruction-Level Abstraction for Hardware
    ACM/ESDA/IEEE Design Automation Conference (DAC), 2018
    [Article]

  • Pramod Subramanyan, Bo-Yuan Huang, Yakir Vizel, Aarti Gupta, and Sharad Malik
    Template-based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018
    [Article] [Code]

2017

  • Shih-Tang Su, Bo-Yuan Huang, Chih-Yu Wang, Che-Wei Teh, and Hung-Yu Wei
    Protocol Design and Game Theoretic Solutions for Device-to-Device Radio Resource Allocation
    IEEE Transactions on Vehicular Technology (TVT), 2017
    [Article]

2015

  • Bo-Yuan Huang, Yi-Hsiang Lai, and Jie-Hong Roland Jiang
    Asynchronous QDI Circuit Synthesis from Signal Transition Protocols
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015
    [Article]

2014

  • Bo-Yuan Huang, Shih-Tang Su, Chih-Yu Wang, Che-Wei Teh, and Hung-Yu Wei
    Resource Allocation in D2D Communication – A Game Theoretic Approach
    IEEE International Conference on Communications Workshops (ICC), 2014
    [Article]

Patents

  • Patrice Godefroid, Bo-Yuan Huang, and Marina Polishchuk
    Intelligently fuzzing data to exercise a service
    US Patent US20210216435A1

Services

  • Tutorial organizer, ISCA, 2022.
  • PC member (Artifact Evaluation Committee), CAV, 2020.
  • External technical reviewer, DAC, 2019.
  • External technical reviewer, DAC, 2017.

Awards

  • ACM TODAES best paper award, 2020
  • Teaching Assistant Award, Princeton, 2019
  • Best in Session Award, TechCon, 2017
  • Full Scholarship, Verification Mentoring Program, CAV, 2016
  • Francis Robbins Upton Fellowship, 2015
  • First Prize in NTUEE Outstanding Undergraduate Independent Research, 2014
  • Second Prize in TSMC Special Research Competition, 2014
  • Ministry of Science and Technology Research Grant, 2013
  • President’s Awards (NTU), 2011, 2012, 2013, 2014
  • First Prize in TSMC Semiconductor Elite Program, 2012
  • First Prize in Microsoft WP Platform Workshop Innovation Award, 2012

Experiences

  • Offensive Security Researcher (Intel Corp., IPAS), 2021 - present
  • Research Intern (Microsoft Research, RiSE), 2019
  • Research Intern (Microsoft Research, RiSE), 2018
  • Security Research Intern (Intel Corp., SeCoE), 2017
  • Technical Intern (Intel Corp., SeCoE), 2016
  • Intern (TSMC, APTG), 2013

Teaching & Mentoring

  • Rematch+ Research Program, 2021
    Parallel SAT Solving with Near and Rapid Clause Sharing
  • Princeton CS Visiting Scholar, 2018
    HDL Synthesis of Instruction-Level Abstraction Models
  • Head preceptor and head lab instructor, 2018
    Contemporary Logic Design
  • Preceptor and lab instructor, 2017
    Contemporary Logic Design
  • Preceptor and lab instructor, 2016
    Contemporary Logic Design
  • Princeton EE Senior Thesis, 2016
    Software/Hardware Co-Verification: Google Verified Boot Firmware with Trusted Platform Module