Welcome to my personal website!

I am a Ph.D. candidate in the Department of Electrical and Computer Engineering at Princeton University, working with Prof. Sharad Malik. Before coming to Princeton, I received my BS in Electrical Engineering and Computer Science from National Taiwan University. My research focuses on the verification and synthesis problems amid the modern accelerator-rich platforms. I worked on the formal modeling and verification methodology for heterogeneous hardware backends. I studied software/hardware co-verification for security assurance in the SoC context. I also developed an end-to-end verifiable compilation flow that allows deep-learning applications to exploit custom accelerators. While most of my works apply formal methods, I am also actively exploring related techniques like simulation-based validation and white/gray/black-box fuzzing.

If you want to know more about me, please take a look at my CV.

News

  • 2021-07-13: Our work on determining architectural state variables in RTL implementations will appear at ICCAD 2021.